Error (10818):vhdl

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Error (10818):vhdl
Error (10818):Can't infer register for "a0[0]" at shiftreg.vhd(96) because it does not hold its value outside the clock edge
PROCESS(clk_in,clk_5)
BEGIN
IF clk_5'EVENT AND clk_5='1' THEN
a16

一个进程process只能检测一个信号边沿,所以会有这样的.
你设计的原意大概是这样的吧：时钟上升沿的的时候采样数据,然后在clk_5的上升沿循环读入数据.
有如下两种处理方法
1.用一个process进行处理,不检测clk_5上升沿,直接检测高电平,但是在给clk_5高电平之前要能够保证a的数据已经是想要得到的数据.
PROCESS(clk_in,clk_5)
BEGIN
IF clk_in'EVENT AND clk_in='1' THEN
a0

Error (10818):vhdl Error (10482): VHDL error at MUX4_1.vhd(18): object "STD_LOG VHDL程序错误 Error (10482):VHDL error at washtop.vhd(33):object vhdl VHDL error at dt.vhd(25):can't determine definition of Error (10327):VHDL error at Vhdl1.vhd(16):can't determine de Error (10500):VHDL syntax error at bijiao.vhd(26) near text Error (10500): VHDL syntax error at cj200.vhd(17) near text Error (10327):VHDL error at xd.vhd(17):can't determine defin Error (10500):VHDL syntax error at cqg.vhd(31) near text ":= Error (10500):VHDL syntax error at biaojue.vhd(16) near text quartusII 运行报错（1）Error (10500):VHDL syntax error at vga.vhd( Error (10334):VHDL error at frame.vhd(6):entity "frame" is u